Recently, multi-core processor systems have taken a form where an independent cache memory is disposed for each core to maintain coherency of the cache memories using a cache coherency mechanism. Hardware executes maintenance of coherency of shared data stored in the cache memories in the multi-core processor system utilizing a cache coherency mechanism and therefore, parallel software for a multi-core processor can be created easily.
The cache coherency mechanism monitors operations of the cache memories and therefore, delay occurs with each access of the cache memory. A technique has been disclosed in which the cache coherency mechanism is controlled based on symmetric multi processing (SMP) or asymmetry multi processing (ASMP) to prevent delay (see, e.g., Japanese Laid-Open Patent Publication No. H10-97465). According to Japanese Laid-Open Patent Publication No. H10-97465, the SMP is employed when plural cores execute plural processes and the ASMP is employed when plural cores execute a single process. A “process” is an execution unit of a program and one or more threads belong to one process. Threads belonging to the same process access the same memory space.
Another technique has been disclosed in which the maintenance of coherency is executed when plural cores execute threads belonging to the same process; and the maintenance of coherency is not executed when the plural cores execute threads each belonging to different processes, respectively (see, e.g., Japanese Laid-Open Patent Publication No. 2004-133753).
A further technique of analyzing dependency relations among threads has been disclosed that generates information indicating access of shared data by executing each thread for each statement and thereby analyzes a dependency relation for each statement of the thread (see, e.g., Japanese Laid-Open Patent Publication No. 2000-207248).
According to the techniques disclosed in the Japanese Laid-Open Patent Publication Nos. H10-97465 and 2004-133753, whether coherency is to be maintained is determined for each process. When numerous functions are not used concurrently such as in an embedded device, coherency is often maintained for a single process. Therefore, even when the techniques according to Japanese Laid-Open Patent Publication Nos. H10-97465 and 2004-133753 are applied to an embedded device, processing to maintain coherency is always executed, whereby operations of the cache coherency mechanism increase. Therefore, problems arise in that delay occurs in the access of the cache memory and increased power consumption results.
When the technique according to Japanese Laid-Open Patent Publication No. 2000-207248 is used, access information of the shared data is analyzed for each statement and therefore, the cache coherency mechanism is controlled for each statement. Consequently, a problem arises in that the number of control sessions significantly increases.